Expand description

This module implement an interpreter for the RISCV32 IM instruction set architecture.

The implementation mostly follows (and copy) code from the MIPS interpreter available here.

Credits

We would like to thank the authors of the following documentations:

https://www.cs.cornell.edu/courses/cs3410/2024fa/assignments/cpusim/riscv-instructions.pdf from the course CS 3410: Computer System Organization and Programming at Cornell University.

The format and description of each instruction is taken from these sources, and copied in this file for offline reference. If you are the author of the above documentations and would like to add or modify the credits, please open a pull request.

For each instruction, we provide the format, description, and the semantic in pseudo-code of the instruction. When signed is mentioned in the pseudo-code, it means that the operation is performed as a signed operation (i.e. signed(v) where v is a 32 bits value means that v must be interpreted as a i32 value in Rust, the most significant bit being the sign - 1 for negative, 0 for positive). By default, unsigned operations are performed.

Structs

Enums

Traits

Functions

  • Interpret an I-type instruction. The encoding of an I-type instruction is as follows:
  • Interpret an M-type instruction. The encoding of an M-type instruction is as follows:
  • Interpret an R-type instruction. The encoding of an R-type instruction is as follows:
  • Interpret an SB-type instruction. The encoding of an SB-type instruction is as follows:
  • Interpret an S-type instruction. The encoding of an S-type instruction is as follows:
  • Interpret an UJ-type instruction. The encoding of an UJ-type instruction is as follows:
  • Interpret an U-type instruction. The encoding of an U-type instruction is as follows: