pub enum MInstruction {
Mul,
Mulh,
Mulhsu,
Mulhu,
Div,
Divu,
Rem,
Remu,
}Expand description
M extension instructions Following https://msyksphinz-self.github.io/riscv-isadoc/html/rvm.html
Variants§
Mul
Format: mul rd, rs1, rs2
Description: performs an 32-bit 32-bit multiplication of signed rs1
by signed rs2 and places the lower 32 bits in the destination register.
Implementation: x[rd] = x[rs1] * x[rs2]
Mulh
Format: mulh rd, rs1, rs2
Description: performs an 32-bit 32-bit multiplication of signed rs1 by
signed rs2 and places the upper 32 bits in the destination register.
Implementation: x[rd] = (x[rs1] * x[rs2]) >> 32
Mulhsu
Format: mulhsu rd, rs1, rs2
Description: performs an 32-bit 32-bit multiplication of signed rs1 by
unsigned rs2 and places the upper 32 bits in the destination register.
Implementation: x[rd] = (x[rs1] * x[rs2]) >> 32
Mulhu
Format: mulhu rd, rs1, rs2
Description: performs an 32-bit 32-bit multiplication of unsigned rs1 by
unsigned rs2 and places the upper 32 bits in the destination register.
Implementation: x[rd] = (x[rs1] * x[rs2]) >> 32
Div
Format: div rd, rs1, rs2
Description: perform an 32 bits by 32 bits signed integer division of
rs1 by rs2, rounding towards zero
Implementation: x[rd] = x[rs1] /s x[rs2]
Divu
Format: divu rd, rs1, rs2
Description: performs an 32 bits by 32 bits unsigned integer division of
rs1 by rs2, rounding towards zero.
Implementation: x[rd] = x[rs1] /u x[rs2]
Rem
Format: rem rd, rs1, rs2
Description: performs an 32 bits by 32 bits signed integer reminder of
rs1 by rs2.
Implementation: x[rd] = x[rs1] %s x[rs2]
Remu
Format: remu rd, rs1, rs2
Description: performs an 32 bits by 32 bits unsigned integer reminder of
rs1 by rs2.
Implementation: x[rd] = x[rs1] %u x[rs2]
Trait Implementations§
Source§impl Clone for MInstruction
impl Clone for MInstruction
Source§fn clone(&self) -> MInstruction
fn clone(&self) -> MInstruction
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more