pub enum RInstruction {
Add,
Sub,
ShiftLeftLogical,
SetLessThan,
SetLessThanUnsigned,
Xor,
ShiftRightLogical,
ShiftRightArithmetic,
Or,
And,
Fence,
FenceI,
}
Variants§
Add
Format: add rd, rs1, rs2
Description: Adds the registers rs1 and rs2 and stores the result in rd. Arithmetic overflow is ignored and the result is simply the low 32 bits of the result.
Sub
Format: sub rd, rs1, rs2
Description: Subs the register rs2 from rs1 and stores the result in rd. Arithmetic overflow is ignored and the result is simply the low 32 bits of the result.
ShiftLeftLogical
Format: sll rd, rs1, rs2
Description: Performs logical left shift on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2.
SetLessThan
Format: slt rd, rs1, rs2
Description: Place the value 1 in register rd if register rs1 is less than register rs2 when both are treated as signed numbers, else 0 is written to rd.
SetLessThanUnsigned
Format: sltu rd, rs1, rs2
Description: Place the value 1 in register rd if register rs1 is less than register rs2 when both are treated as unsigned numbers, else 0 is written to rd.
Xor
Format: xor rd, rs1, rs2
Description: Performs bitwise XOR on registers rs1 and rs2 and place the result in rd
ShiftRightLogical
Format: srl rd, rs1, rs2
Description: Logical right shift on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2
ShiftRightArithmetic
Format: sra rd, rs1, rs2
Description: Performs arithmetic right shift on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2
Or
Format: or rd, rs1, rs2
Description: Performs bitwise OR on registers rs1 and rs2 and place the result in rd
And
Format: and rd, rs1, rs2
Description: Performs bitwise AND on registers rs1 and rs2 and place the result in rd
Fence
Format: fence
Description: Used to order device I/O and memory accesses as viewed by other RISC-V harts and external devices or coprocessors. Any combination of device input (I), device output (O), memory reads (R), and memory writes (W) may be ordered with respect to any combination of the same. Informally, no other RISC-V hart or external device can observe any operation in the successor set following a FENCE before any operation in the predecessor set preceding the FENCE.
FenceI
Format: fence.i
Description: Provides explicit synchronization between writes to instruction memory and instruction fetches on the same hart.
Trait Implementations§
Source§impl Clone for RInstruction
impl Clone for RInstruction
Source§fn clone(&self) -> RInstruction
fn clone(&self) -> RInstruction
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source
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