pub enum IInstruction {
Show 15 variants
LoadByte,
LoadHalf,
LoadWord,
LoadByteUnsigned,
LoadHalfUnsigned,
ShiftLeftLogicalImmediate,
ShiftRightLogicalImmediate,
ShiftRightArithmeticImmediate,
SetLessThanImmediate,
SetLessThanImmediateUnsigned,
AddImmediate,
XorImmediate,
OrImmediate,
AndImmediate,
JumpAndLinkRegister,
}
Variants§
LoadByte
Format: lb rd, offset(rs1)
Description: Loads a 8-bit value from memory and sign-extends this to 32 bits before storing it in register rd.
LoadHalf
Format: lh rd, offset(rs1)
Description: Loads a 16-bit value from memory and sign-extends this to 32 bits before storing it in register rd.
LoadWord
Format: lw rd, offset(rs1)
Description: Loads a 32-bit value from memory and sign-extends this to 32 bits before storing it in register rd.
LoadByteUnsigned
Format: lbu rd, offset(rs1)
Description: Loads a 8-bit value from memory and zero-extends this to 32 bits before storing it in register rd.
LoadHalfUnsigned
Format: lhu rd, offset(rs1)
Description: Loads a 16-bit value from memory and zero-extends this to 32 bits before storing it in register rd.
ShiftLeftLogicalImmediate
Format: slli rd, rs1, shamt
Description: Performs logical left shift on the value in register rs1 by the shift amount held in the lower 5 bits of the immediate
ShiftRightLogicalImmediate
Format: srli rd, rs1, shamt
Description: Performs logical right shift on the value in register rs1 by the shift amount held in the lower 5 bits of the immediate
ShiftRightArithmeticImmediate
Format: srai rd, rs1, shamt
Description: Performs arithmetic right shift on the value in register rs1 by the shift amount held in the lower 5 bits of the immediate
SetLessThanImmediate
Format: slti rd, rs1, imm
Description: Place the value 1 in register rd if register rs1 is less than the signextended immediate when both are treated as signed numbers, else 0 is written to rd.
SetLessThanImmediateUnsigned
Format: sltiu rd, rs1, imm
Description: Place the value 1 in register rd if register rs1 is less than the immediate when both are treated as unsigned numbers, else 0 is written to rd.
AddImmediate
Format: addi rd, rs1, imm
Description: Adds the sign-extended 12-bit immediate to register rs1. Arithmetic overflow is ignored and the result is simply the low 32 bits of the result. ADDI rd, rs1, 0 is used to implement the MV rd, rs1 assembler pseudo-instruction.
XorImmediate
Format: xori rd, rs1, imm
Description: Performs bitwise XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd Note, “XORI rd, rs1, -1” performs a bitwise logical inversion of register rs1(assembler pseudo-instruction NOT rd, rs)
OrImmediate
Format: ori rd, rs1, imm
Description: Performs bitwise OR on register rs1 and the sign-extended 12-bit immediate and place the result in rd
AndImmediate
Format: andi rd, rs1, imm
Description: Performs bitwise AND on register rs1 and the sign-extended 12-bit immediate and place the result in rd
JumpAndLinkRegister
Format: jalr rd, rs1, imm
Description: Jump to address and place return address in rd.
Trait Implementations§
Source§impl Clone for IInstruction
impl Clone for IInstruction
Source§fn clone(&self) -> IInstruction
fn clone(&self) -> IInstruction
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source
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