Function layout 

fn layout<F: PrimeField>() -> [Vec<Box<dyn WitnessCell<F>>>; 4]

Witness layout

• The values and cell contents are in little-endian order. This is important for compatibility with other gates, where elements of the first 7 columns could be copied and reused by them. So they should be in the usual little-endian witness byte order.
• Limbs are mapped to columns so that those containing the MSBs are in lower numbered columns (i.e. big-endian column mapping). This is important so that copy constraints are possible on the MSBs. For example, we can convert the RangeCheck0 circuit gate into a 64-bit lookup by adding two copy constraints to constrain columns 1 and 2 to zero.